A positive edge-triggered flip-flop changes its state when ________________
Select correct option:
Enable input (EN) is set
Preset input (PRE) is set
Low-to-high transition of clock
High-to-low transition of clock
If S=1 and R=1, for negative edge triggered flip-flop then Q(t+1) = _________
Select correct option:
0
1
Invalid
Input
isinvalid
Question # 1 of 10 ( Start time: 09:48:01 AM )
Total M - 1
The ABEL symbol for “OR” operation is
Select correct option:
&
!
#
$
Question # 2 of 10 ( Start time: 09:48:22 AM )
Total M - 1
Adjacent 1s detector circuit will have active low output for the input
Select correct option:
1101
1010
0110
1011
Question # 3 of 10 ( Start time: 09:49:03 AM )
Total M - 1
A 5-variable karnaugh map has
Select correct option:
sixteen cells
thirty two cells
sixty-four cells
None of these
In asynchronous digital systems all the circuits change their state with respect to a common clock
Select correct option:
True
False
Divide-by-32 counter can be acheived by using
Select correct option:
Flip-Flop and DIV 10
Flip-Flop and DIV 16
Flip-Flop and DIV 32
DIV 16 and DIV 32
The Synchronous counters are also known as Ripple Counters:
Select correct option:
True
False ok
A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power dissipation of the flip-flop is
Select correct option:
10 mW
25 mW
64 mW
1024 mW
__________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.
► Race condition
► Clock Skew
► Ripple Effect
► None of given options
Question No: 22 ( M - 1 ) .
Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter counts upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), now suppose that the present state is “1100” and X=1, the next state of the counter will be ___________
► 0000
► 1101
► 1011
► 1111
Question No: 23 ( M - 1 ) .
In a state diagram, the transition from a current state to the next state is determined by
► Current state and the inputs
► Current state and outputs
► Previous state and inputs
► Previous state and outputs
Question No: 24 ( M - 1 ) .
________ is used to simplify the circuit that determines the next state.
► State diagram
► Next state table
► State reduction
► State assignment
Question No: 25 ( M - 1 ) .
A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register.
► 1
► 2
► 4
► 8
Question No: 26 ( M - 1 ) .
Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)
► 1100
► 0011
► 0000
► 1111
Flip flops are also called _____________
Select correct option:
Bi-stable multivibrators
Bi-stable singlevibrators
Bi-stable dualvibrators
Bi-stable transformer
A counter is implemented using three (3) flip-flops, possibly it will have ________ maximum output status.
Select correct option:
3
7
8
15
A mono -stable device only has a single stable state
Select correct option:
True
False
When the both inputs of edge-triggered J-K flop-flop are set to logic zero _________
Select correct option:
The flop-flop is triggered
Q=0 and Q’=1
Q=1 and Q’=0
The output of flip-flop remains unchanged
A transparent mode means _____________
Select correct option:
The changes in the data at the inputs of the latch are seen at the output
The changes in the data at the inputs of the latch are not seen at the output
Propagation Delay is zero (Output is immediately changed when clock signal is applied)
Input Hold time is zero (no need to maintain input after clock transition)
The _____________ input overrides the ________ input
Select correct option:
Asynchronous, synchronous
Synchronous, asynchronous
Preset input (PRE), Clear input (CLR)
Clear input (CLR), Preset input (PRE)
Divide-by-160 counter is acheived by using
Select correct option:
Flip-Flop and DIV 10
Flip-Flop and DIV 16
DIV 16 and DIV 32
DIV 16 and DIV 10
The Decimal- to- BCD Encoder has
_______ outputs
Select correct option :
2
4
10
16
An Astable multivibrator is known as a(n) _______
Select correct option:
Oscillator
Booster
One-shot
Dual-shot
Three cascaded modulus-10 counters have an overall modulus of
Select correct option:
30
100
1000
10000
The Synchronous counters are also known as Ripple Counters:
Select correct option:
True
False
The counter states or the range of numbers of a counter is determined by the formula. (“n” represents the total number of flip-flops)
Select correct option:
(n raise to power 2 )
(n raise to power 2 and then minus 1)
(2 raise to power n)
(2 raise to power n and then minus 1)
RCO stands for __________
Select correct option:
Reconfiguration Counter Output
Ripple Counter Output
Reconfiguration Clock Output
Ripple Clock Output
A counter is implemented using three (3) flip-flops, possibly it will have ________ maximum output status.
Select correct option:
3
7
8
15
If a circuit suffers “Clock Skew “ problem, the output of circuit can’t be guarantied.
Select correct option:
True
False
When the both inputs of edge-triggered J-K flop-flop are set to logic zero _________
Select correct option:
The flop-flop is triggered
Q=0 and Q’=1
Q=1 and Q’=0
The output of flip-flop remains unchanged
A positive edge-triggered flip-flop changes its state when ________________
Select correct option:
Enable input (EN) is set
Preset input (PRE) is set
Low-to-high transition of clock
High-to-low transition of clock
We have a digital circuit. Different parts of circuit operate at different clock frequencies (4 MHZ, 2 MHZ and 1 MHZ), but we have a single clock source having a fix clock frequency (4MHZ), to supply the required frequency to each part of circuit, we can get help by using ___________
Select correct option:
Using S-R Flop-Flop
D-flipflop
J-K flip-flop
T-Flip-Flop
Demultiplexer can also be used as
Select correct option :
Deselector
Decoder
Distribuiter
Encoder
Each stage of Master-slaveflip- flop works at ____ of the clocksignal
Select correct option:
Each stage works on complete clocksignal
One fourth
One third
One half
A modulus-14 counter has fourteen states requiring_____________
Select correct option:
14 Flip Flops
14 Registers
4 Flip Flops
4 Registers
The minimum time required for the input logic levels to remain stable before the clock transition occurs is known as the ___________
Select correct option:
Set-up time
Hold time
Pulse Interval time
Pulse Stability time (PST)
In a 4-bit binary counter, the next state after the terminal count in the DOWN mode is ____________
Select correct option:
0000
1111
0001
10000
________ flip-flops are obsolete now.
Select correct option:
Edge-triggered
Master-Slave
T-Flipflop
D-Flipflop
A mono -stable device only has a single stable state
Select correct option:
True
False
A decade counter is __________
Select correct option:
Mod- 3 counter
Mod- 5 counter
Mod- 8 counter
Mod- 10 counter
An Astable multivibrator is known as a (n) _______
Select correct option:
Oscillator
Booster
One-shot
Dual-shot
A synchronous decade counter will have _______flip-flops
Select correct option:
3
4
7
10
The glitches due to "Race Condition" canbe avoided by using a ___________
Select correct option:
Gated flip-flops
Pulse triggered flip-flops
Positive-Edge triggered flip-flops
Negative-Edge triggered flip- flops
The operation of J-K flip-flop issimilar to that of the SR flip-flop except that the J- K flip-flop ___________
Select correct option:
Doesn’ t have an invalid state
Sets to clear whenboth J = 0 and K = 0
It does notshow transition on change in pulse
It does notaccept asynchronous inputs
Divide- by-32 counter can be acheived by using
Select correct option:
Flip-Flop and DIV 10
Flip-Flop and DIV 16
Flip-Flop and DIV 32
DIV 16 and DIV 32
The voltage gain of the Inverting Amplifier is given by the relation ________
► Vout / Vin = - Rf / Ri
► Vout / Rf = - Vin / Ri
► Rf / Vin = - Ri / Vout
► Rf / Vin = Ri / Vout
Question No: 15 ( M - 1 ) .
LUT is acronym for _________
► Look Up Table
► Local User Terminal
► Least Upper Time Period
► None of given options
Question No: 16 ( M - 1 ) .
The three fundamental gates are ___________
► AND, NAND, XOR
► OR, AND, NAND
► NOT, NOR, XOR
► NOT, OR, AND
Question No: 17 ( M - 1 ) .
The total amount of memory that is supported by any digital system depends upon ______
► The organization of memory
► The structure of memory
► The size of decoding unit
► The size of the address bus of the microprocessor
Question No: 18 ( M - 1 ) .
Stack is an acronym for _________
► FIFO memory
► LIFO memory
► Flash Memory
► Bust Flash Memory
Question No: 19 ( M - 1 ) .
Addition of two octal numbers “36” and “71” results in ________
► 213
► 123
► 127
► 345
Question No: 20 ( M - 1 ) .
___________ is one of the examples of synchronous inputs.
► J-K input
► EN input
► Preset input (PRE)
► Clear Input (CLR)
A 4- bit UP/DOWN counter isin DOWN mode and in the 1010 state. on the next clockpulse, to what state does the counter go ?
Select correct option:
1001
1011
0011
1100
8 - bit parallel data can be converted
into serial data by using ________
multiplexer
Select correct option :
4 - to- 2
4 - to- 4
8 - to- 1
8 - to- 4
____________is said to occur when multiple internal variables change due to change in oneinput variable
Select correct option:
Hold and Wait
Clock Skew
Racecondition
Hold delay
InMaster-Slave flip-flop setup, the master flip flop operates at __________
Select correct option:
Positive half cycleof pulse
Negative half cycle of pulse
Both Master-Slave operate simultaneously
Master- Slave flip- flop does notoperate on pulses, rather it isedge triggered.
A negative edge-triggered flip-flop changes its state when________________
Select correct option:
Enable input (EN) is set
Preset input (PRE) isset
Low- to-high transition of clock
High-to-low transition of clock
Flip flops are also called _____________
Select correct option:
Bi- stable multivibrators
Bi- stable singlevibrators
Bi- stable dualvibrators
Bi- stable transformer
___________is oneof the examples of asynchronous inputs.
Select correct option:
J-K input
S-R input
D input
Clear Input (CLR)
The terminal count of a 4-bit binary counter in the DOWN mode is ____________
Select correct option:
0000
0011
1100
1111
The terminal count of a 4-bit binary counter in the UP mode is ____________
Select correct option:
1100
0011
1111
0000
____________is said to occur when multiple internal variables change due to change in oneinput variable
Select correct option:
Hold and Wait
Clock Skew
Race condition
Hold delay
If a circuit suffers “Clock Skew “ problem, the output of circuit can ’ t be guarantied.
Select correct option:
True
False
The minimum time for which the input
signal has to be maintained at the
input of flip - flop is called ______ of
the flip - flop .
Set - up time
Hold time 242
Pulse Interval time
Pulse Stability time (PST)
The glitches due to " Race Condition"
can be avoided by using a ___________
Gated flip - flops
Pulse triggered flip - flops
Positive - Edge triggered flip - flops
Negative- Edge triggered flip - flops
267
For a 3 - to- 8 decoder how many 2 -
to- 4 decoders will be required?
Select correct option :
4
3
2
1
We have a digital circuit . Different
parts of circuit operate at different
clock frequencies ( 4 MHZ , 2 MHZ and
1 MHZ ), but we have a single clock
source having a fix clock frequency
(4 MHZ ) , to supply the required
frequency to each part of circuit , we
can get help by using ___________
Using
S- R Flop- Flop
D - flipflop
J - K flip - flop
T- Flip - Flop
Once the state diagram is drawn for
any sequential circuit the next step is
to draw
Transiation table
Karnaugh map
Next- state table 306
Logic expression
A synchronous decade counter will have
_______ flip - flops
3 ,
7 ,
4 ,
10
For a gated D - Latch if EN= 1 and D = 1
then Q ( t + 1 ) =
0 ,
1 ,
Q( t )
valid
Demultiplexer can also be used as
Select correct option :
Deselector
Decoder
Distribuiter
Encoder
If a circuit suffers “ Clock Skew “
problem, the output of circuit can ’ t be
guarantied .
True
false
The 74 HC 163 is a 4 - bit Synchronous
Counter .it has . .... ... ... ...parallel data
inputs pins
2
,4
,6
,8
The _____________ input overrides the
________ input
Asynchronous, synchronous 235
Synchronous, asynchronous
Preset input (PRE ) , Clear input ( CLR )
Clear input ( CLR ), Preset input ( PRE )
A standard interface for programming
the In - System PLD consists of
2 wire ,
4 wire 194
8 wire ,
16 wire
signal has to be maintained at the
input of flip - flop is called ______ of
the flip - flop .
Set - up time
Hold time 242
Pulse Interval time
Pulse Stability time (PST)
The glitches due to " Race Condition"
can be avoided by using a ___________
Gated flip - flops
Pulse triggered flip - flops
Positive - Edge triggered flip - flops
Negative- Edge triggered flip - flops
267
For a 3 - to- 8 decoder how many 2 -
to- 4 decoders will be required?
Select correct option :
4
3
2
1
We have a digital circuit . Different
parts of circuit operate at different
clock frequencies ( 4 MHZ , 2 MHZ and
1 MHZ ), but we have a single clock
source having a fix clock frequency
(4 MHZ ) , to supply the required
frequency to each part of circuit , we
can get help by using ___________
Using
S- R Flop- Flop
D - flipflop
J - K flip - flop
T- Flip - Flop
Once the state diagram is drawn for
any sequential circuit the next step is
to draw
Transiation table
Karnaugh map
Next- state table 306
Logic expression
A synchronous decade counter will have
_______ flip - flops
3 ,
7 ,
4 ,
10
For a gated D - Latch if EN= 1 and D = 1
then Q ( t + 1 ) =
0 ,
1 ,
Q( t )
valid
Demultiplexer can also be used as
Select correct option :
Deselector
Decoder
Distribuiter
Encoder
If a circuit suffers “ Clock Skew “
problem, the output of circuit can ’ t be
guarantied .
True
false
The 74 HC 163 is a 4 - bit Synchronous
Counter .it has . .... ... ... ...parallel data
inputs pins
2
,4
,6
,8
The _____________ input overrides the
________ input
Asynchronous, synchronous 235
Synchronous, asynchronous
Preset input (PRE ) , Clear input ( CLR )
Clear input ( CLR ), Preset input ( PRE )
A standard interface for programming
the In - System PLD consists of
2 wire ,
4 wire 194
8 wire ,
16 wire
Bi- stable devices remain in either of
their _________ states unless the
inputs force the device to switch its
state
Select correct option :
Ten
Eight
Three
Two
In Synchronous systems, the output of
all the digital circuits changes when an
enable signal is applied instead of the
clock signal.
Select correct option :
True
False (Page No . 228)
________ flip - flops are obsolete now .
Select correct option :
Edge - triggered
Master - Slave (Page No . 257 )
T - Flipflop
D - Flipflop
If a circuit suffers “ Clock Skew “
problem, the output of circuit can ’ t be
guarantied .
Select correct option :
True
False
Flip flops are also called
_____________
Select correct option :
Bi- stable multivibrators ( Page No.
228)
Bi- stable singlevibrators
Bi- stable dualvibrators
Bi- stable transformer
A mono- stable device only has a single
stable state
Select correct option :
True ( Page No. 262 )
False
If S = 1 and R = 0 , then for positive edge
triggered flip - flop Q ( t + 1 ) =
_________
Select correct option :
0
1 ( Page No. 230 )
Invalid
Input is invalid
If the S and R inputs of the gated S - R
latch are connected together using a
______ gate then there is only a single
input to the latch . The input is
represented by D instead of S or R ( A
gated D - Latch)
Select correct option :
AND
OR
NOT ( Page No. 226 )
XOR
In Master - Slave flip - flop the Clock
signal is connected to Slave flip - flip
using ________ gate
Select correct option :
AND
OR
NOT
NAND
The glitches due to " Race Condition"
can be avoided by using a ___________
Select correct option :
Gated flip - flops
Pulse triggered flip - flops
Positive - Edge triggered flip - flops
Negative - Edge triggered flip - flops
(Page No . 267 )
The boolean expression ( A + C) (AB '
+ AC )( A 'C ' + B ')can be simplified to
Select correct option :
AB '
AB + A 'C
A 'B + BC
AB + BC
19. The 4-bit 2’s complement representation of “+5” is _____________
►1010
►1110
►1011
►0101
20. Which of the number is not a representative of hexadecimal system
►1234
►ABCD
►1001
►DEHF Hexa does not have H as remainder
____________ is said to occur when multiple internal variables change due to change in one input variable
Select correct option:
Hold and Wait
Clock Skew
Race condition
Hold delay
How many data select lines are
required for selecting eight inputs ?
Select correct option :
4
3
2
1
8 - bit parallel data can be converted
into serial data by using ________
multiplexer
Select correct option :
4 - to- 2
4 - to- 4
8 - to- 1
8 - to- 4
On a Karnaugh map , grouping the 0 s
produces
Select correct option :
a POS expression
a SOP expression
a " don 't care " condition
AND- OR logic
Adjacent 1 s detector circuit will have
active high output for the input
Select correct option :
0101
1010
0011
0001
The bolean expression A + BC equals
Select correct option :
(A ' + B )( A ' + C)
(A + B )( A + C )
(A + B )( A' + C )
none of the above
Adjacent 1 s detector circuit will have
active low output for the input
Select correct option :
1101
1010
0110
1011
In a 4 - variable K - map , a 2 - variable
product term is produced by
Select correct option :
a 2 - cell group of 1 s
a 8 - cell group of 1 s
a 4 - cell group of 1 s
a 4 - cell group of 0 s
The Decimal- to- BCD Encoder has
_______ outputs
Select correct option :
2
4
10
16
In a 4 - variable K - map , a 2 - variable
product term is produced by
Select correct option :
a 2 - cell group of 1 s
a 8 - cell group of 1 s
a 4 - cell group of 1 s
a 4 - cell group of 0 s
Half- Adder Logic circuit contains
_____ XOR Gates .
Select correct option :
0
2
4
6
Adjacent 1 s detector circuit will have
active low output for the input
Select correct option :
1101
1010
0110
1011
A 5 - variable karnaugh map has
Select correct option :
sixteen cells
thirty two
cells
sixty - four cells
None of these
8 - bit parallel data can be converted
into serial data by using ________
multiplexer
Select correct option :
4 - to- 2
4 - to- 4
8 -
to- 1
8 - to- 4
For a 3 - to- 8 decoder how many 2 -
to- 4 decoders will be required?
Select correct option :
4
3
2
1
2 ' s complement of 5 is
Select correct option :
1101
1011
0101
1100
The Decimal- to- BCD Encoder has
_______ outputs
Select correct option :
2
4
10
16
In a 4 - variable K - map , a 2 - variable
product term is produced by
Select correct option :
a 2 - cell group of 1 s
a 8 - cell group of 1 s
a 4 - cell group of 1 s
a 4 - cell group of 0 s
Half- Adder Logic circuit contains
_____ XOR Gates .
Select correct option :
0
2
4
6
Adjacent 1 s detector circuit will have
active low output for the input
Select correct option :
1101
1010
0110
1011
A 5 - variable karnaugh map has
Select correct option :
sixteen cells
thirty two
cells
sixty - four cells
None of these
8 - bit parallel data can be converted
into serial data by using ________
multiplexer
Select correct option :
4 - to- 2
4 - to- 4
8 -
to- 1
8 - to- 4
____________ is said to occur when multiple internal variables change due to change in one input variable
► Clock Skew
► Race condition
► Hold delay
► Hold and Wait
Question No: 8 ( M - 1 ) .
The _____________ input overrides the ________ input
► Asynchronous, synchronous
► Synchronous, asynchronous
► Preset input (PRE), Clear input (CLR)
► Clear input (CLR), Preset input (PRE)
Question No: 9 ( M - 1 ) .
A decade counter is __________.
► Mod-3 counter
► Mod-5 counter
► Mod-8 counter
► Mod-10 counter
Question No: 10 ( M - 1 ) .
In asynchronous transmission when the transmission line is idle, _________
► It is set to logic low
► It is set to logic high
► Remains in previous state
► State of transmission line is not used to start transmission
Question No: 11 ( M - 1 ) .
A Nibble consists of _____ bits
► 2
► 4
► 8
► 16
Question No: 12 ( M - 1 ) .
The output of this circuit is always ________.
► 1
► 0
► A
►
Question No: 13 ( M - 1 ) .
Excess-8 code assigns _______ to “-8”
► 1110
► 1100
► 1000
► 0000
For a 3 - to- 8 decoder how many 2 -
to- 4 decoders will be required?
Select correct option :
4
3
2
1
Asynchronous mean that_____________
Select correct option:
Each flip-flop after the first one is enabled by the output of the preceding flip-flop
Each flip-flop is enabled by the output of the preceding flip-flop
Each flip-flop except the last one is enabled by the output of the preceding flip-flop
Each alternative flip-flop after the first one is enabled by the output of the preceding flip-flop
2 ' s complement of 5 is
Select correct option :
1101
1011
0101
1100
The Decimal- to- BCD Encoder has
_______ outputs
Select correct option :
2
4
10
16
In a 4 - variable K - map , a 2 - variable
product term is produced by
Select correct option :
a 2 - cell group of 1 s
a 8 - cell group of 1 s
a 4 - cell group of 1 s
a 4 - cell group of 0 s
2 ' s complement of 5 is
Select correct option :
1101
1011
0101
1100
Half- Adder Logic circuit contains
_____ XOR Gates .
Select correct option :
0
2
4
6
In a 4-bit binary counter, the next state after the terminal count in the DOWN mode is ____________
Select correct option:
0000
1111
0001
10000
Adjacent 1 s detector circuit will have
active low output for the input
Select correct option :
1101
1010
0110
1011
8 - bit parallel data can be converted
into serial data by using ________
multiplexer
Select correct option :
4 - to- 2
4 - to- 4
8 -
to- 1
8 - to- 4
A 5 - variable karnaugh map has
Select correct option :
sixteen cells
thirty two
cells
sixty - four cells
None of these
Demultiplexer can also be used as
Select correct option :
Deselector
Decoder
Distribuiter
Encoder
Half- Adder Logic circuit contains
_____ XOR Gates .
Select correct option :
0
2
4
6
Question # 4 of 10 ( Start time: 09:49:35 AM )
Total M - 1
the boolean expression AB'CD'is
Select correct option:
a sumterm
a product term
a literal term
always 1
Question # 5 of 10 ( Start time: 09:50:08 AM )
Total M - 1
On a Karnaugh map, grouping the 0s produces
Select correct option:
a POS expression
a SOP expression
a "don't care" condition
AND-OR logic
Question # 6 of 10 ( Start time: 09:50:30 AM )
The bolean expression A + BC equals
Select correct option:
)A' + B)(A' + C)
(A + B)(A + C)
(A + B)(A' + C)
none of the above
Question # 7 of 10
Total M - 1
8-bit parallel data can be converted into serial data by using ________ multiplexer
Select correct option:
4-to-2
4-to-4
8-to-1
8-to-4
A 5 - variable karnaugh map has
Select correct option :
sixteen cells
thirty two cells
sixty - four cells
None of these
Question # 8 of 10
Total M - 1
which of the following rules states that if one input of an AND gate is always 1, the output is equal to the other input?
Select correct option:
A +1 =1
A +A =A
A.A = A
A.1 = A
Question # 9 of 10
the boolean expression A + B' + C is
Select correct option:
a sum term
a literal term
a product term
a complemented term
Question # 10 of 10
An example of SOP expression is
Select correct option:
A + B(C + D)
A'B + AC' + AB'C
(A' + B + C)(A + B' + C)
both (a) nad (b)
8 - bit parallel data can be converted
into serial data by using ________
multiplexer
Select correct option :
4 - to- 2
4 - to- 4
8 - to- 1
8 - to- 4
8 - bit parallel data can be converted
into serial data by using ________
multiplexer
Select correct option :
4 - to- 2
4 - to- 4
8 - to- 1
8 - to- 4
8 - bit parallel data can be converted
into serial data by using ________
multiplexer
Select correct option :
4 - to- 2
4 - to- 4
8 - to- 1
8 - to- 4
2 ' s complement of 5 is
Select correct option :
1101
1011
0101
1100
On a Karnaugh map , grouping the 0 s
produces
Select correct option :
a POS expression
a SOP expression
a " don 't care " condition
AND- OR logic
For a 3 - to- 8 decoder how many 2 -
to- 4 decoders will be required?
Select correct option :
4
3
2
1
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