A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register.
► 1
► 2
► 4
► 8
Question No: 2 ( M - 1 ) .
In a sequential circuit the next state is determined by ________ and _______
► State variable, current state
► Current state, flip-flop output
► Current state and external input
► Input and clock signal applied
Question No: 3 ( M - 1 ) .
The divide-by-60 counter in digital clock is implemented by using two cascading counters:
► Mod-6, Mod-10
► Mod-50, Mod-10
► Mod-10, Mod-50
► Mod-50, Mod-6
Question No: 4 ( M - 1 ) .
In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained.
► True
► False
Question No: 5 ( M - 1 ) .
The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop.
► Set-up time
► Hold time
► Pulse Interval time
► Pulse Stability time (PST)
Question No: 6 ( M - 1 ) .
74HC163 has two enable input pins which are _______ and _________
► ENP, ENT
► ENI, ENC
► ENP, ENC
► ENT, ENI
The bolean expression A + BC equals
Select correct option :
(A ' + B )( A ' + C)
(A + B )( A + C )
(A + B )( A' + C )
none of the above
Adjacent 1 s detector circuit will have
active high output for the input
Select correct option :
0101
1010
0011
0001
How many data select lines are
required for selecting eight inputs ?
Select correct option :
4
3
2
1
Which of the number is not a
representative of hexadecimal system
Select correct option :
1234
ABCD
1001
DEFH
In case of cascading Integrated
Circuit counters, the enable inputs and
RCOof the Integrated Circuit counters
allow cascading of multiple counters
together
Select correct option :
True
False
High level Noise Margins ( VNH ) of
CMOS 5 volt series circuits is
_____________
Select correct option :
0 . 3 V
0 . 5 V
0 . 9 V
3 . 3 V
To get the answer “ 1 ” in Boolean
addition of three variables , ________
Select correct option :
All three variables must be 1
One of the variables must be 1
All three variables must be 0
Any two variables must be 1
The 3 - variable Karnaugh Map ( K- Map )
has _______ cells for min or max terms
Select correct option :
4
8
12
16
________ is invalid number of cells in a
single group formed by the adjacent
cells in K - map
Select correct option :
2
8
12
16
The boolean expression A + B' + C is
a sum term
a literal term
a product term
a complemented term
Consider A= 1 ,B = 0 , C= 1 . A, B and C
represent the input of three bit NAND
gate the output of the NAND gate will
be _____
Select correct option :
Zero
One
Undefined
No output as input is invalid
The Binary number 1011 .101 has an
Integer part represented by _____ and
a fraction part ____ separated by a
decimal point .
Select correct option :
1011, 101
101, 1011
101, 1101
10111, 11
LUT is acronym for _________
► Look Up Table
► Local User Terminal
► Least Upper Time Period
► None of given options
. Question No: 28 ( M - 1 ) .
The diagram given below represents __________
► Demorgans law
► Associative law
► Product of sum form
► Sum of product form
Question No: 29 ( M - 1 ) .
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________
► Doesn’t have an invalid state
► Sets to clear when both J = 0 and K = 0
► It does not show transition on change in pulse
► It does not accept asynchronous inputs
Question No: 30 ( M - 1 ) .
A multiplexer with a register circuit converts _________
► Serial data to parallel
► Parallel data to serial
► Serial data to serial
► Parallel data to parallel
Question No: 31 ( M - 1 ) .
A GAL is essentially a ________.
► Non-reprogrammable PAL
► PAL that is programmed only by the manufacturer
► Very large PAL
► Reprogrammable PAL
Adding two octal numbers “ 36 ” and
“ 71 ” result in ________
Select correct option :
213
123
127
345
The OR Gate performs a Boolean
_______ function
Select correct option :
Addition correct
Subtraction
Multiplication
Division
Adding two octal numbers “ 36 ” and
“ 71 ” result in ________
Select correct option :
213
123
127
345
If we multiply “ 723 ” and “ 34 ” by
representing them in floating point
notation i .e . by first , converting them
in floating point representation and
then multiplying them, the value of
mantissa of result will be ________
Select correct option :
24 .582
2 . 4582
24582 not sure
0 . 24582
NOR Gate can be used to perform the
operation of AND, OR and NOT Gate
Select correct option :
TRUE
FALSE
The three fundamental gates are
___________
Select correct option :
AND, NAND, XOR
OR , AND, NAND
NOT, NOR , XOR
NOT, OR , AND
If two numbers in BCD representation
generate an invalid BCD number then
the binary ________ is added to the
result
Select correct option :
1001
0110
1111
1100
A SOP expression having a domain of 3
variables will have a truth table having
____ combinations of inputs and
corresponding output values .
Select correct option :
2
4
8
16
In designing any counter the transition
from a current state to the next sate
is determined by
Select correct option :
Current state and inputs
Only inputs
Only current state
current state and outputs
The 4 - variable K - Map has ________
rows and ___________ columns of cells .
Select correct option :
2 , 2
2 , 4
4 , 2
4 , 4NAND gate is form by connecting
_________
Select correct option :
AND Gate and then NOT Gate correct
NOT Gate and then AND Gate
AND Gate and then OR Gate
OR Gate and then AND Gate
A standard SOP form has __________
terms that have all the variables in the
domain of the expression.
Sum
A synchronous decade counter will
have _____ flip - flops
Select correct option :
3
4
7
10
.Which one of the following is not a
valid rule of Boolean algebra?
(a ) A + 1 = 1
(b ) A = Ā
(c ) A. A = A
(d ) A + 0 = A
How many data select lines are
required for selecting eight inputs ?
1
2
3
4
If two adjacent 1 s are detected in the
input , the output is set to high .
input combinations will be
0011
0101
1100
1010
The output of the expression F=A.B.C will be Logic ________ when A=1, B=0, C=1. ► Undefined ► One ► Zero ► No Output as input is invalid.
CS302 Question No: 5 ( M - 1 ) ________ is invalid number of cells in a single group formed by the adjacent cells in K-map.
► 2 ► 8
► 12 ► 16
► 12 ► 16
CS302 Question No: 6 ( M - 1 ) The PROM consists of a fixed non-programmable ____________ Gate array configured as a decoder. ► AND ► OR ► NOT ► XOR
CS302 Question No: 7 ( M - 1 ) ___________ is one of the examples of synchronous inputs.
► J-K input
► EN input
► Preset input (PRE)
► Clear Input (CLR)
► J-K input
► EN input
► Preset input (PRE)
► Clear Input (CLR)
The 4 - variable Karnaugh Map (K - Map )
has ______ rows and ____colums
2 , 2
4 , 4
4 , 2
2 , 4
the boolean expression AB 'CD 'is
a sumterm
a product term
a literal term
always 1
Don’ t care conditions are marked as
___________ in the output column of
the function table
0
1
X
None of the given options
An example of SOP expression is
A + B (C + D )
A' B + AC ' + AB ' C
(A ' + B + C )( A + B ' + C )
both ( a ) and (b )
For a Standard SOP expression , a
______ is placed in the cell
corresponding to the product term
(Minterm ) present in the expression.
0
1 (ans )
X (don ’ t care condition )
In a 4 - bit binary counter , the next
state after the terminal count in the
DOWN mode is __________
Select correct option :
0000
1111
0001
10000
A SOP expression having a domain of 3
variables will have a truth table having
____ combinations of inputs and
corresponding output values .
Select correct option :
2
4
8
16
The OR Gate performs a Boolean
_______ function
Select correct option :
Addition
Subtraction
Multiplication
Division
Sum term ( Max term ) is implemented
using ________ gates
Select correct option :
OR
AND
NOT
OR - AND
Above is the circuit diagram of _______. ► Asynchronous up-counter
► Asynchronous down-counter
► Synchronous up-counter
► Synchronous down-counter
► Asynchronous down-counter
► Synchronous up-counter
► Synchronous down-counter
CS302 Question No: 26 ( M - 1 ) The sequence of states that are implemented by a n-bit Johnson counter is
► n+2 (n plus 2) ► 2n (n multiplied by 2) ► 2n (2 raise to power n) ► n2 (n raise to power 2)
► n+2 (n plus 2) ► 2n (n multiplied by 2) ► 2n (2 raise to power n) ► n2 (n raise to power 2)
The number “ 1259” may belong to
_______ number system .
Select correct option :
Binary number system
Octal or Decimal system .
Decimal or Hexadecimal system
Binary or Hexadecimal system
“ 1101 ” in signed representation is
equivalent to _______
Select correct option :
10
13
- 10
- 5
TTL based devices work with a dc
supply of ____ Volts
Select correct option :
+ 10
+ 5
+ 3
3 . 3
In decimal value “ 275 ” the weight of
the digit “ 7 ” is ___________
Select correct option :
0
1
10
100
The decimal “ 10 ” will have an octal
equivalent ________
Select correct option :
9
10
11
12
Caveman number system is Base
______ number system
Select correct option :
2
5
10
16
The terminal count of a 4 - bit binary
counter in the DOWN mode
is_ _________
Select correct option :
0000
0011
1100
1111
A divide- by- 10 ring counter requires a
minimum of
Select correct option :
ten flip - flops
five flip - flops
four flip - flops
twelve flip - flops
In moore machine the output depends
on
Select correct option :
the current state and the output of
previous flip flop
only inputs
the current state
When an eight bit serial in / serial out
shift register is used for a 24 micro
seconds time delay , the clock
frequenct must be
Select correct option :
41 .67 KHz
333 KHz
125 KHz
8 MHz
To parallel load a byte of data into a
shift register , there must be
Select correct option :
one clock pulse
one clock pulse for each 1 in the data
eight clock pulse
one clock pulse for each 0 in the data
Divide - by- 160 counter is acheived by
using
Select correct option :
Flip - Flop and DIV 10
Flip - Flop and DIV 16
DIV 16 and DIV 32
DIV 16 and DIV 10
With a 100 KHz clock frequency , eight
bits can be serially entered into a shift
register in
Select correct option :
80 micro seconds
8 micro seconds
80 mili seconds
10 micro seconds
1011+ 101 = ______
Select correct option :
10000
00001
10011
11001
Once the state diagram is drawn for
any sequential circuit the next step is
to draw
Select correct option :
Transiation table
Karnaugh map
Next- state table
Logic expression
When an eight bit serial in / serial out
shift register is used for a 24 micro
seconds time delay , the clock
frequenct must be
Select correct option :
41 .67 KHz
333 KHz Not Confirm
125 KHz
8 MHz
A 4 - bit binary up / down counter is in
the binary state of zero . The next
state in the DOWN mode is :
Select correct option :
0001
1000
1110
1111
In moore machine the output depends
on
Select correct option :
the current state and the output of
previous flip flop
only inputs
the current state
the current state and inputs
A divide- by- 10 Johnson counter
requires
Select correct option :
ten flip - flops
four flip - flops
five flip - flops
twelve flip - flops
Number of states in an 8 - bit Johnson
counter sequence are :
Select correct option :
8
12
14
16
In a 4 - bit binary counter , the next
state after the terminal count in the
DOWN mode is _ _ _ _ _ _ _ _ _ _ _ _
Select correct option :
0000
1111
0001
10000
Divide - by- 32 counter can be acheived
by using
Select correct option :
Flip - Flop and DIV 10
Flip - Flop and DIV 16
Flip - Flop and DIV 32
DIV 16 and DIV 32
A 4 - bit binary up / down counter is in
the binary state of zero . The next
state in the UP mode is
Select correct option :
0001
1000
1110
1111
Three cascaded modulus - 10 counters
have an overall modulus of
Select correct option :
30
100
1000
10000
shift register is used for a 24 micro
seconds time delay , the clock
frequenct must be
Select correct option :
41 .67 KHz
333 KHz Not Confirm
125 KHz
8 MHz
A 4 - bit binary up / down counter is in
the binary state of zero . The next
state in the DOWN mode is :
Select correct option :
0001
1000
1110
1111
In moore machine the output depends
on
Select correct option :
the current state and the output of
previous flip flop
only inputs
the current state
the current state and inputs
A divide- by- 10 Johnson counter
requires
Select correct option :
ten flip - flops
four flip - flops
five flip - flops
twelve flip - flops
Number of states in an 8 - bit Johnson
counter sequence are :
Select correct option :
8
12
14
16
In a 4 - bit binary counter , the next
state after the terminal count in the
DOWN mode is _ _ _ _ _ _ _ _ _ _ _ _
Select correct option :
0000
1111
0001
10000
Divide - by- 32 counter can be acheived
by using
Select correct option :
Flip - Flop and DIV 10
Flip - Flop and DIV 16
Flip - Flop and DIV 32
DIV 16 and DIV 32
A 4 - bit binary up / down counter is in
the binary state of zero . The next
state in the UP mode is
Select correct option :
0001
1000
1110
1111
Three cascaded modulus - 10 counters
have an overall modulus of
Select correct option :
30
100
1000
10000
The first Least Most digit in decimal
number system has
Select correct option :
Has position 0 and weight equal to 1
not sure
Has position 1 and weight equal to 0
Has position 1 and weight equal to 10
Has position 0 and weight equal to 10
A stage in the shift register consists
of
Select correct option :
a latch
a flip flop
a byte of storage
four bits of storage
When an eight bit serial in / serial out
shift register is used for a 24 micro
seconds time delay , the clock
frequenct must be
Select correct option :
41 .67 KHz
333 KHz not confirm
125 KHz
8 MHz
Divide - by- 160 counter is acheived by
using
Select correct option :
Flip - Flop and DIV 10
Flip - Flop and DIV 16
DIV 16 and DIV 32
DIV 16 and DIV 10
A 4 - bit UP / DOWN counter is in DOWN
mode and in the 1010 state . on the
next clock pulse , to what state does the
counter go ?
Select correct option :
1001
1011
0011
1100
In moore machine the output depends
on
Select correct option :
the current state and the output of
previous flip flop
only inputs
the current state
the current state and inputs
A divide- by- 10 Johnson counter
requires
Select correct option :
ten flip - flops
four flip - flops
five flip - flops
twelve flip - flops
Three cascaded modulus - 10 counters
have an overall modulus of
Select correct option :
30
100
1000
10000
Question No: 4 ( M - 1 ) .
An alternate method of implementing Comparators which allows the Comparators to be easily cascaded without the need for extra logic gates is _______
► Using a single comparator
► Using Iterative Circuit based Comparators
► Connecting comparators in vertical hierarchy
► Extra logic gates are always required.
Question No: 5 ( M - 1 ) .
Demultiplexer is also called
► Data selector
► Data router
► Data distributor
► Data encoder
Question No: 6 ( M - 1 ) .
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________
► Doesn’t have an invalid state
► Sets to clear when both J = 0 and K = 0
► It does not show transition on change in pulse
► It does not accept asynchronous inputs
Question No: 7 ( M - 1 ) .
A positive edge-triggered flip-flop changes its state when ________________
► Low-to-high transition of clock
► High-to-low transition of clock
► Enable input (EN) is set
► Preset input (PRE) is set
A divide- by- 10 ring counter requires a
minimum of
Select correct option :
ten flip - flops
five flip - flops
four flip - flops
twelve flip - flops
Number of states in an 8 - bit Johnson
counter sequence are :
Select correct option :
8
12
14
16
the terminal count of a modulus - 13
binary counter is
Select correct option :
0000
1111
1101
1100
A Divide - by- 20 counter can be
acheived by using
Select correct option :
Flip - Flop and DIV 10
Flip - Flop and DIV 16
Flip - Flop and DIV 32
Div 10 and DIV 16
To serially shift a byte of data into a
shift register , there must be
Select correct option :
one clock pulse
one load pulse
eight clock pulses
one clock pulse for each 1 in the data
In moore machine the output depends
on
Select correct option :
the current state and the output of
previous flip flop
only inputs
the current state
the current state and inputs
1
A divide- by- 10 Johnson counter
requires
Select correct option :
ten flip - flops
four flip - flops
five flip - flops
twelve flip - flops
Three cascaded modulus - 10 counters
have an overall modulus of
Select correct option :
30
100
1000
10000
A 4 - bit binary up / down counter is in
the binary state of zero . The next
state in the DOWN mode is :
Select correct option :
0001
1000
1110
1111
A divide- by- 10 ring counter requires a
minimum of
Select correct option :
ten flip - flops
five flip - flops
four flip - flops
twelve flip - flops
A multiplexer with a register circuit
converts
Select correct option :
Serial data to parallel
Parallel data to serial
Serial data to serial
Parallel data to parallel
In designing any counter the transition
from a current state to the next sate
is determined by
Select correct option :
Current state and inputs
Only inputs
Only current state
current state and outputs
A decade counter can be implemented
by truncating the counting sequence of
a MOD - 20 counter .
Select correct option :
True
False
The terminal count of a 4 - bit binary
counter in the DOWN mode
is_ _________
Select correct option :
0000
0011
1100
1111
An Asynchronous Down - counter is
implemented (Using J - K flip - flop) by
connecting ______
Select correct option :
output of all flip - flops to clock
input of next flip - flops
output of
all flip - flops to clock input of next
flip - flops
output of all flip - flops to J input of
next flip - flops
output of all flip - flops to K input
of next flip - flops
the terminal count of a modulus - 13
binary counter is
Select correct option :
0000
1111
1101
1100
A decade counter can be implemented
by truncating the counting sequence of
a MOD - 20 counter .
Select correct option :
True
False
A 4 - bit UP / DOWN counter is in DOWN
mode and in the 1010 state . on the
next clock pulse , to what state does the
counter go ?
Select correct option :
1001
1011
0011
1100
Design of state diagram is one of
many steps used to design
Select correct option :
a clock
a truncated counter
an UP /DOWN counter
any counter
An Astable multivibrator is known as a
(n ) _____
Select correct option :
Oscillator
Booster
One - shot
Dual- shot
The glitches due to " Race Condition"
can be avoided by using a _________
Select correct option :
Gated flip - flops
Pulse triggered flip - flops
Positive - Edge triggered flip -
flops
Negative - Edge triggered flip -
flops
Karnaugh map is used in designing
Select correct option :
a clock
a counter
an UP /DOWN counter
All of the above
__________ is said to occur when
multiple internal variables change due
to change in one input variable
Select correct option :
Hold and Wait
Clock Skew
Race condition
Hold delay
Three cascaded modulus - 10
counters have an overall modulus of
Select correct option :
30
100
1000
10000
An Astable multivibrator is known
as a (n ) _____
Select correct option :
Oscillator
Booster
One - shot
Dual- shot
__________occurs when the same
clock signal arrives at different times
at different clock inputs due to
propagation delay .
Select correct option :
Race condition
Clock Skew
Ripple Effect
None of given options
The glitches due to " Race Condition"
can be avoided by using a _________
Select correct option :
Gated flip - flops
Pulse triggered flip - flops
Positive - Edge triggered flip -
flops
Negative - Edge triggered flip -
flops
A flip - flop is presently in SET
stae and must remain SET on the next
cliock pulse . What must j and K be ?
Select correct option :
J = 1 , K = 0
J = 1 , K = X ( Don't care )
J = X( Don't care ), K = 0
J = 0 , K = X ( Don't care )
The Synchronous counters are also
known as Ripple Counters :
Select correct option :
True
False
The Synchronous counters are also
known as Ripple Counters :
Select correct option :
True
False
__________occurs when the same clock
signal arrives at different times at
different clock inputs due to
propagation delay .
Select correct option :
Race condition
Clock Skew
Ripple Effect
None of given options
Divide - by- 160 counter is acheived by
using
Select correct option :
Flip - Flop and DIV 10
Flip - Flop and DIV 16
DIV 16 and DIV 32
DIV 16 and DIV 10
Design of state diagram is one of
many steps used to design
Select correct option :
a clock
a truncated counter
an UP /DOWN counter
any counter
__________ Counters as the name
indicates are not triggered
simultaneously
Select correct option
Asynchronous
Synchronous
Positive - Edge triggered
Negative- Edge triggered
Ripple Clock Output
The 74 HC 163 is a 4 - bit Synchronous
Counter .it has . .... ... ... ...data output pins
Select correct option :
2
4
6
8
A counter is implemented using three
(3 ) flip - flops , possibly it will
have ______ maximum output status .
Select correct option :
3
7
8
15
Sum term ( Max term ) is implemented
using ________ gates
Select correct option :
OR
AND
NOT
OR - AND
Design of state diagram is one of
many steps used to design
Select correct option :
a clock
a truncated counter
an UP /DOWN counter
any counter
Divide - by- 32 counter can be acheived
by using
Select correct option :
Flip - Flop and DIV 10
Flip - Flop and DIV 16
Flip - Flop and DIV 32
DIV 16 and DIV 32
The counter states or the range of
numbers of a counter is determined by
the formula . (“n ” represents the total
number of flip - flops )
Select correct option :
(n raise to power 2 )
(n raise to power 2 and then minus 1 )
(2 raise to power n )
(2 raise to power n and then minus 1 )
A 4 - bit UP / DOWN counter is in DOWN
mode and in the 1010 state . on the
next clock pulse , to what state does the
counter go ?
Select correct option :
1001
1011
0011
1100
A 4 - bit binary UP / DOWN counter is in
the binary state zero . the next state in
the DOWN mode is_ __________
Select correct option :
0001
1111
1000
1110
Divide - by- 160 counter is acheived by
using
Select correct option :
Flip - Flop and DIV 10
Flip - Flop and DIV 16
DIV 16 and DIV 32
DIV 16 and DIV 10
A counter is implemented using three
(3 ) flip - flops , possibly it will
have ______ maximum output status .
Select correct option :
3
7
8
15
RCO stands for ________
Select correct option :
Reconfiguration Counter Output
Ripple Counter Output
Reconfiguration Clock Output
Ripple Clock Output
__________occurs when the same clock
signal arrives at different times at
different clock inputs due to
propagation delay .
Select correct option :
Race condition
Clock Skew
Ripple Effect
None of given options
For a down counter that counts from
(111 to 000 ), if current state is " 101 "
the next state will be _______
Select correct option :
111
110
010
none of given options
A Divide - by- 20 counter can be
acheived by using
Select correct option :
Flip - Flop and DIV 10
Flip - Flop and DIV 16
Flip - Flop and DIV 32
Div 10 and DIV 16
by using
Select correct option :
Flip - Flop and DIV 10
Flip - Flop and DIV 16
Flip - Flop and DIV 32
DIV 16 and DIV 32
The counter states or the range of
numbers of a counter is determined by
the formula . (“n ” represents the total
number of flip - flops )
Select correct option :
(n raise to power 2 )
(n raise to power 2 and then minus 1 )
(2 raise to power n )
(2 raise to power n and then minus 1 )
A 4 - bit UP / DOWN counter is in DOWN
mode and in the 1010 state . on the
next clock pulse , to what state does the
counter go ?
Select correct option :
1001
1011
0011
1100
A 4 - bit binary UP / DOWN counter is in
the binary state zero . the next state in
the DOWN mode is_ __________
Select correct option :
0001
1111
1000
1110
Divide - by- 160 counter is acheived by
using
Select correct option :
Flip - Flop and DIV 10
Flip - Flop and DIV 16
DIV 16 and DIV 32
DIV 16 and DIV 10
A counter is implemented using three
(3 ) flip - flops , possibly it will
have ______ maximum output status .
Select correct option :
3
7
8
15
RCO stands for ________
Select correct option :
Reconfiguration Counter Output
Ripple Counter Output
Reconfiguration Clock Output
Ripple Clock Output
__________occurs when the same clock
signal arrives at different times at
different clock inputs due to
propagation delay .
Select correct option :
Race condition
Clock Skew
Ripple Effect
None of given options
For a down counter that counts from
(111 to 000 ), if current state is " 101 "
the next state will be _______
Select correct option :
111
110
010
none of given options
A Divide - by- 20 counter can be
acheived by using
Select correct option :
Flip - Flop and DIV 10
Flip - Flop and DIV 16
Flip - Flop and DIV 32
Div 10 and DIV 16
Design of state diagram is one of
many steps used to design
Select correct option :
a clock
a truncated counter
an UP /DOWN counter
any counter
An Astable multivibrator is known as a
(n ) _____
Select correct option :
Oscillator
Booster
One - shot
Dual- shot
___________ is one of the examples of asynchronous inputs.
► J-K input
► S-R input
► D input
► Clear Input (CLR)
► J-K input
► S-R input
► D input
► Clear Input (CLR)
CS302 Question No: 9 ( M - 1 ) The _____________ input overrides the ________ input. ► Asynchronous, synchronous ► Synchronous, asynchronous ► Preset input (PRE), Clear input (CLR) ► Clear input (CLR), Preset input (PRE)
CS302 Question No: 10 ( M - 1 ) __________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. ► Race condition ► Clock Skew ► Ripple Effect ► None of given options
CS302 Question No: 11 ( M - 1 ) Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter counts upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), now suppose that the present state is “1100” and X=1, the next state of the counter will be ___________
► 0000
► 1101
► 1011
► 1111
► 0000
► 1101
► 1011
► 1111
CS302 Question No: 12 ( M - 1 ) In a state diagram, the transition from a current state to the next state is determined by ► Current state and the inputs ► Current state and outputs ► Previous state and inputs ► Previous state and outputs
CS302 Question No: 13 ( M - 1 ) ________ is used to minimize the possible no. of states of a circuit. ► State assignment ► State reduction ► Next state table ► State diagram
The glitches due to " Race Condition"
can be avoided by using a _________
Select correct option :
Gated flip - flops
Pulse triggered flip - flops
Positive - Edge triggered flip - flops
Negative- Edge triggered flip - flops
A decade counter is ________
Select correct option :
Mod - 3 counter
Mod - 5 counter
Mod - 8 counter
Mod - 10 counter
The terminal count of a 4 - bit binary
counter in the DOWN mode
is_ _________
Select correct option :
0000
0011
1100
1111
The Synchronous counters are also
known as Ripple Counters :
Select correct option :
True
False
__________occurs when the same clock
signal arrives at different times at
different clock inputs due to
propagation delay .
Select correct option :
Race condition
Clock Skew
Ripple Effect
None of given options
Divide - by- 160 counter is acheived by
using
Select correct option :
Flip - Flop and DIV 10
Flip - Flop and DIV 16
DIV 16 and DIV 32
DIV 16 and DIV 10
Design of state diagram is one of
many steps used to design
Select correct option :
a clock
a truncated counter
an UP /DOWN counter
any counter
12. 3-to-8 decoder can be used to implement Standard SOP and POS Boolean expressions
►True (Page 160)
►False
13. The device shown here is most likely a _______
►Comparator
►Multiplexer
►Demultiplexer click here for detail
►Parity generator
14. The GAL22V10 has ____ inputs
►22 (Page 195)
►10
►44
►20
15. A latch retains the state unless
►Power is turned off
►Input is changed (page 218)
►Output is changed
►Clock pulse is changed
16. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input
goes to 0, the latch will be ________.
►SET (Page 220)
►RESET
►Clear
►Invalid
17. Consider a circuit consisting of two consecutive NOT gates, the entire circuit belongs to a CMOS
5 Volt series, if certain voltage is applied on the input, the output voltage of Logic high signal
(VoH) will be in the range of _______ volts.
►4 to 4.5
►4.5 to 5
►0 to 4.5
►0 to 3.5
18. A.(B.C) = (A.B).C is an expression of __________
►Demorgan‟s Law
►Distributive Law
►Commutative Law
►Associative Law (Page 72)
In a 4 - bit binary counter , the next
state after the terminal count in the
DOWN mode is __________
Select correct option :
0000
1111
0001
10000
A 5 - variable karnaugh map has
Select correct option :
sixteen cells
thirty two cells
sixty- four cells
None of these
The bolean expression A + BC equals
Select correct option :
(A ' + B )( A' + C )
(A + B ) (A + C )
(A + B ) (A ' + C )
none of the above
the boolean expression AB 'CD 'is
Select correct option :
a sumterm
a product term
a literal term
always 1
The OR Gate performs a Boolean _______ function
►Addition (Page 42)
►Subtraction
►Multiplication
►Division
4. TTL based devices work with a dc supply of ____ Volts
►+10
►+5 (Page 61)
►+3
►3.3
5. A standard POS form has __________ terms that have all the variables in the domain of the
expression.
►Sum (Page 85)
►Product
►Min
►Composite
6. A SOP expression having a domain of 3 variables will have a truth table having ____
combinations of inputs and corresponding output values.
►2
►4
►8 (According to rule)
►16
7. A BCD to 7-Segment decoder has
►3 inputs and 7 outputs
►4 inputs and 7 outputs (Page 103)
►7 inputs and 3 outputs
► inputs and 4 outputs
8. In the Karnaugh map shown above, which of the loops shown represents a legal grouping?
►A
►
►C click here for detail
►D
9. The binary value of 1010 is converted to the product term
►True
►False
Which one of the following is NOT a
valid rule of Boolean algebra?
Select correct option :
A + 1 = 1
A = A '
AA = A
A + 0 = A
In a 4 - variable K - map , a 2 - variable
product term is produced by
Select correct option :
a 2 - cell group of 1 s
a 8 - cell group of 1 s
a 4 - cell group of 1 s
a 4 - cell group of 0 s
On a Karnaugh map , grouping the 0 s
produces
Select correct option :
a POS expression
a SOP expression
a " don ' t care " condition
AND- OR logic
A 3 - variable karnaugh map has
Select correct option :
eight cells
three cells
sixteen cells
four cells
which of the following rules states
that if one input of an AND gate is
always 1 , the output is equal to the
other input ?
Select correct option :
A + 1 = 1
A + A = A
A. A = A
A. 1 = A
2 ' s complement of 5 is
Select correct option :
1101
1011
0101
1100
An example of SOP expression is
Select correct option :
A + B (C + D )
A' B + AC ' + AB ' C
(A ' + B + C )( A + B ' + C )
both ( a ) nad (b )
2's complement of any binary number can be calculated by
► adding 1's complement twice
► adding 1 to 1's complement (Page 144)
► subtracting 1 from 1's complement.
► calculating 1's complement and inverting Most significant bit
Question No: 15 ( Marks: 1 ) - Please choose one
The binary value “1010110” is equivalent to decimal __________
► 86 (According to formula)
► 87
► 88
► 89
Question No: 16 ( Marks: 1 ) - Please choose one
Tri-State Buffer is basically a/an _________ gate.
► AND
► OR
► NOT
► XOR (Page 186)
MIDTERM EXAMINATION 2010
1. The binary value “11011” is equivalent to __________
►1B (According to rule)
►1C
►1D
►1E
2. An important application of AND Gate is its use in counter circuit
►True (Page 281)
►False
Adjacent 1 s detector circuit will have
active low output for the input
Select correct option :
1101
1010 ( Not Confirm )
0110
1011
The complement of a variable is always
Select correct option :
0
1
equal to the variable
the inverse of the variable
Adjacent 1 s detector circuit will have
active high output for the input
Select correct option :
0101
1010
0011
0001
The domain of the expression AB 'CD +
AB ' + C 'D + B is
Select correct option :
A and D
B only
A, B, C and D
none of these
the boolean expression A + B ' + C is
Select correct option :
a sum term
a literal term
a product term
a complemented term
The boolean expression ( A + C) (AB ' +
AC ) (A 'C ' + B ') can be simplified to
Select correct option :
AB '
AB + A' C
A' B + BC
AB + BC
The boolean expression X = AB + CD
represents
Select correct option :
two ORs ANDed together
a 4 - input AND gate
two ANDs ORed together
an exclusive - Or
Which one of the following is NOT a
valid rule of Boolean algebra?
Select correct option :
A + 1 = 1
A = A '
AA = A
A + 0 = A
The function to be performed by the processor is selected by set of inputs known as ________
► Function Select Inputs (Page 147)
► MicroOperation selectors
► OPCODE Selectors
► None of given option
Question No: 10 ( Marks: 1 ) - Please choose one
For a 3-to-8 decoder how many 2-to-4 decoders will be required?
► 2 (Page 160)
► 1
► 3
► 4
Question No: 11 ( Marks: 1 ) - Please choose one
GAL is an acronym for ________.
► Giant Array Logic
► General Array Logic (Page 183)
► Generic Array Logic
► Generic Analysis Logic
Question No: 12 ( Marks: 1 ) - Please choose one
The Quad Multiplexer has _____ outputs
► 4 (Page 216)
► 8
► 12
► 16
Question No: 13 ( Marks: 1 ) - Please choose one
A.(B.C) = (A.B).C is an expression of __________
► Demorgan‟s Law
► Distributive Law
► Commutative Law
► Associative Law (Page 72)
How many data select lines are
required for selecting eight inputs ?
Select correct option :
4
3
2
1
the boolean expression AB 'CD 'is
a sumterm
a product term
a literal term
always 1
The boolean expression ( A + C ) ( AB'
+AC ) ( A 'C ' + B ') can be simplified to
AB '
AB + A 'C
A' B + BC
AB + BC
which of the following rules states
that if one input of an AND gate is
always 1 , the output is equal to the
other input ?
A + 1 =1
A + A = A
A. A = A
A .1 = A
The range of Excess-8 code is from ______ to ______
► +7 to -8 (Page 34)
► +8 to -7
► +9 to -8
► -9 to +8
Question No: 5 ( Marks: 1 ) - Please choose one
A non-standard POS is converted into a standard POS by using the rule _____
►
►
AA = 0 (Page 85)
►
► A+B = B+A
Question No: 6 ( Marks: 1 ) - Please choose one
The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
► 4
► 8 (Page 89)
► 12
► 16
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